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<span id="Condition-Code-Status"></span><h3 class="section">18.15 Condition Code Status</h3>
<span id="index-condition-code-status"></span>

<p>Condition codes in GCC are represented as registers,
which provides better schedulability for
architectures that do have a condition code register, but on which
most instructions do not affect it.  The latter category includes
most RISC machines.
</p>
<p>Implicit clobbering would pose a strong restriction on the placement of
the definition and use of the condition code.  In the past the definition
and use were always adjacent.  However, recent changes to support trapping
arithmetic may result in the definition and user being in different blocks.
Thus, there may be a <code>NOTE_INSN_BASIC_BLOCK</code> between them.  Additionally,
the definition may be the source of exception handling edges.
</p>
<p>These restrictions can prevent important
optimizations on some machines.  For example, on the IBM RS/6000, there
is a delay for taken branches unless the condition code register is set
three instructions earlier than the conditional branch.  The instruction
scheduler cannot perform this optimization if it is not permitted to
separate the definition and use of the condition code register.
</p>
<p>If there is a specific
condition code register in the machine, use a hard register.  If the
condition code or comparison result can be placed in any general register,
or if there are multiple condition registers, use a pseudo register.
Registers used to store the condition code value will usually have a mode
that is in class <code>MODE_CC</code>.
</p>
<p>Alternatively, you can use <code>BImode</code> if the comparison operator is
specified already in the compare instruction.  In this case, you are not
interested in most macros in this section.
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